1 DS950 ( ) June 9, Sample1 Copyright 2018 2021 xilinx , Inc., xilinx , the xilinx logo, Alveo, Artix, Kintex, Spartan, Versal , Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of xilinx in the United States and other countries. AMBA, AMBA Designer, Arm, ARM1176JZ-S, CoreSight, Cortex, and PrimeCell are trademarks of Arm in the EU and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective DescriptionVersal devices are the industry's first adaptive compute acceleration platform (ACAP), combining adaptable processing and acceleration engines with programmable logic and configurable connectivity to enable customized, heterogeneous hardware solutions for a wide variety of applications in data Center, Automotive, 5G Wireless, Wired, and Defense.
2 Versal ACAPs feature transformational features like an integrated silicon host interconnect shell and Intelligent Engines (AI and DSP), Adaptable Engines, and Scalar Engines, providing superior performance/watt over conventional FPGAs, CPUs, and GPUs. AI Edge Series: Designed with safety in mind, this series delivers an adaptive technology platform that combines high AI inference performance, low latency, and power efficiency for edge Core Series: The high-compute series with medium density programmable logic and connectivity capability coupled with AI and DSP acceleration Series: The mid-range series with medium density programmable logic, signal processing, and connectivity Series: The high-end, high bandwidth series, rich in networking interfaces, security engines, and providing high compute ComparisonsVersal Architecture andProduct data sheet : OverviewDS950 ( ) June 9, 2021 Engineering SampleTable 1.
3 Device ResourcesVersal ACAP Resources and CapabilitiesAI Edge SeriesAI Core SeriesPrime SeriesPremium SeriesProgrammable Network on Chip (NoC) Aggregate INT8 TOPs7 22857 2288 5736 206 System Logic Cells (K)44 1,139540 1,968329 2,2331,575 7,352 Hierarchical Memory (Mb)40 17790 19154 282198 994 DSP Engines90 1,312928 1,968464 3,9841,904 14,352AI Engines8 304128 400 Processing System Serial Transceivers0 448 448 4848 168 Max. Serial Bandwidth (full duplex) (Tb/s) 530478 770316 770586 780 Memory Controllers1 32 41 43 4 Versal Architecture and Product data sheet : OverviewDS950 ( ) June 9, Sample2 Summary of FeaturesArchitectureVersal ACAPs are built around an integrated shell composed of a programmable network on chip (NoC), which enables seamless memory-mapped access to the full height and width of the device.
4 ACAPs comprise: a multicore scalar processing system (PS); an integrated block for PCIe with DMA and Cache Coherent Interconnect Designs (CPM); SIMD VLIW AI Engine accelerators for artificial intelligence and complex signal processing; and Adaptable Engines in the programmable logic (PL). Together, these form a platform for fast time-to-market (TTM) compute acceleration for cloud, edge, and networking applications. The platform management controller (PMC), adjacent to the PS, is responsible for booting and configuring the device. Versal devices typically have I/O and memory controllers on the north and south edges of the device and serial transceivers on the east and west edges.
5 The NoC spans full height and width of the device. Compute and AccelerationThe Versal AI Core series has an array of signal processing cores that are highly optimized for functions in machine learning, convolutional neural networks, wireless radio, backhaul, cable, and radar applications. The array consists of a number of AI Engines, each comprising a 32-bit scalar RISC processor, fixed and floating point vector units, data memory, and interconnect. AI Engines can be used as a single tile, as the complete array, or at any granularity in between. The creation of custom acceleration and compute engines in the AI Engine array is done at a high-level through C and C++.Every Versal ACAP has Scalar Engines that comprise a dual-core Arm Cortex -A72 (APU) and a dual-core Arm Cortex-R5F (RPU) in the PS.
6 The PS includes a number of peripherals for communication standards, including gigabit Ethernet and USB , and controllers for SPI, I2C, UART, and CAN-FD. The PS accesses the DDR memory controllers on the top and bottom of the device through the NoC. In addition to interfacing to external memory, the APU includes: Level 2 (L2) cache; the RPU includes tightly coupled memory (TCM); and both APU and RPU have access to the on-chip memory (OCM).The PL is made up of configurable logic blocks, containing 6-input look-up tables (LUTs) and flip-flops; different-sized memory blocks; 36Kb block RAM and 288Kb UltraRAM; digital signal processing (DSP) blocks; and a wealth of interconnect, switches, and muxes to connect blocks together.
7 All resources are arranged in columns. The PL is divided into regions that are a fixed height. Each region has its own clocking capabilities and NoC access Management The PMC resides adjacent to, but is independent from, the PS. It is responsible for the boot and configuration of the device from the primary boot source. The PMC is also responsible for configuring the PL, which can be configured before or after the PS. It also controls encryption, authentication, system monitoring, and device debug capabilities of the south edge of the Versal ACAPs typically contains a number of XPIO banks and associated memory controllers to read from and write to DDR4 and LPDDR4 memory.
8 XPIO can be used independently from the dedicated memory controllers for many functions, including any with soft memory controllers created in the PL. The east and west edges of the device typically contain serial transceivers capable of communicating up to 112Gb/s. The PL can also contain integrated blocks for high-value functions, such as the integrated block for PCIe (PL PCIE) with support for Compute Express Link (CXL), multirate Ethernet MAC, 600G Ethernet MAC, 600G Interlaken, and 400G High-Speed Crypto (HSC) Architecture and Product data sheet : OverviewDS950 ( ) June 9, Sample3 Feature SummaryTable 2: Versal AI Edge SeriesVE2002VE2102VE2202VE2302VE2602VE17 52VE2802AI Engines-ML8 1224341520304AI Engines000003040AI Engine data Memory (Mb)4612177676152 DSP Engines901763244649841,3121,312 System Logic Cells43,75080,080229,688328,720820,31398 1,1201,139,040 CLB Flip-Flops40,00073,216210,000300,544750, 000897,0241,041,408 LUTs20,00036,608105,000150,272375,000448 ,512520,704 Distributed RAM (Mb) RAM Blocks2447108155476954600 Block RAM (Mb) Blocks2447108155224462264 UltraRAM (Mb) RAM (Mb)
9 32323232000 APUDual-core Arm Cortex-A72, 48KB/32KB L1 Cache w/ parity 1MB L2 Cache w/ ECCRPUDual-core Arm Cortex-R5F, 32KB/32KB L1 Cache, and 256KB TCM w/ECCM emory256KB On-Chip Memory w/ECCC onnectivityEthernet (x2); UART (x2); CAN-FD (x2); USB (x1); SPI (x2); I2C (x2)NoC Master / Slave Ports2255212121 DDR Bus Width64646464192192192 DDR Memory Controllers1111333 PCIe w/DMA & CCIX (CPM) 1 x Gen4x16, CCIX1 x Gen4x16, CCIX1 x Gen4x16, CCIXPCIe (PL PCIE) 1 x Gen4x81 x Gen4x84 x Gen4x84 x Gen4x84 x Gen4x840G Multirate Ethernet MAC0011222 XPIO216216216216486486486 HDIO002222444444 GTY Transceivers ( )00000440 GTYP Transceivers ( )008832032 Versal Architecture and Product data sheet : OverviewDS950 ( ) June 9, Sample4 Table 3: Versal AI Edge Series.
10 Device-Package Combinations and Maximum I/OVE2002VE2102VE2202VE2302VE2602VE1752V E2802 XPIO, HDIOMIO, GTYPXPIO, HDIOMIO, GTYPXPIO, HDIOMIO, GTYPXPIO, HDIOMIO, GTYPXPIO, HDIOMIO, GTYPXPIO, HDIOMIO, GTYPXPIO, HDIOMIO, GTYPSBVA484114, 078, 0114, 078, 0 SBVA625216, 078, 0216(1), 078, 0 SFVA784216, 078, 0216(1), 078, 0216, 2278, 8216(1), 2278, 8 VSVG1369378, 4478, 24 VSVH1369324, 4478, 32324, 4478, 32 VSVA1596378(2), 4478, 32 VFVB1596486, 4478, 32486, 4478, 32 VSVA2197486, 4478, 44 Notes: 1. 132 XPIO are dedicated for DDR memory LPDDR4 is supported in 324 I/O Architecture and Product data sheet : OverviewDS950 ( ) June 9, Sample5 Table 4: Versal AI Core SeriesVC1352VC1502VC1702VC1802VC1902VC26 02VC2802AI Engines12824830430040000AI Engines-ML00000152304AI Engine data Memory (Mb)32627675100152152 DSP Engines9281,3121,3121,6001,9689841,312 System Logic Cells539,840797,440981,1201,585,9381,968 ,400820,3131,139,040 CLB Flip-Flops493,568729,088897,0241,450,000 1,799,680750,0001,041,408 LUTs246,784364,544448,512725,000899,8403 75,000520,704 Distributed RAM (Mb) RAM Blocks441547954800967476600 Block RAM (Mb) Blocks209215462325463224264 UltraRAM (Mb) RAM (Mb)32000000 APUDual-core Arm Cortex-A72; 48KB/32KB L1 Cache w/ parity and ECC; 1MB L2 Cache w/ ECCRPUDual-core Arm Cortex-R5F.
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